Intel 14th Generation Meteor Lake Rumors

CPU 14th Generation Meteor Lake Rumor Intel

Last updated on January 7, 2023

Intel 14th Gen Meteor Lake-S Rumored to Be Canceled

The much-anticipated Intel 14th generation CPU Meteor Lake-S (MTL-S) is rumored to be canceled. The rumor was recently leaked by two sources close to Intel, according to Youtuber Moore’s Law Is Dead.  The leakers claim the desktop version of Meteor Lake (Non-S Version) is still on its way but, will have substantially less under the hood than anticipated. Mobile devices may still get the original version of MTL on schedule in Q4 2023. 

The rumor is very disappointing since the 14th generation chip was said to be around 22% faster clock speeds, with a 40% power reduction than its predecessor Raptor Lake.  A great upgrade for anyone with an Intel 11th generation CPU or below.  

Why is Meteor Lake-S Canceled? 

The reasons behind the cancellation of Meteor Lake-S are vague. The rumors indicate Intel is experiencing problems with the Intel 4 node process which is on a, newly used, 7 nanometers architecture.  As outsiders, we can only speculate on the challenges Intel is encountering. It is likely the cancellation of Meteor Lake-S may have to do with the myriad of changes expected to be in Intel’s 14th generation CPU.

Size Matters 10nm to 7nm Process

As mentioned earlier, Intel is changing their node process from Intel 7 to Intel 4.  Intel 4 is based on a 7nm architecture process, boosted with Intel’s best practices (Through the balancing of power, performance and efficiency).  The number “4” in “Intel 4”, refers to real life nanometers.  So even though Intel is using a 7nm process, the way Intel manufacturers at that size results in performance you would expect, using a normal 4nm process.  This implies Intel has more stringent guidelines already in place for a 7nm process. 

Raptor Lake, Intel’s 13th generation CPU, was created with Intel 7 (10nm), so they have essentially cut the size of their process node by a third for Meteor Lake.  That isn’t much when it comes to counting money but, when talking about 10 billionths of a meter to 7 billionths of a meter, the complexities could be hard to foreshadow. The smaller architecture will undoubtedly create some challenges with the manufacturing process of MTL.  

3D Chip Stacking Tech – Foverus Omni And Foverus Direct

Foverus Omni (FO) and Foverus Direct (FD) , very simply stated, are technologies that help Intel stack multiple dies on top of each other, with power and spatial efficiency.  These technologies allow Intel to move from building their chips from 2D to 3D, much like going from building a one-story house to a multi-story house.  The need for these technologies is important if Intel wants to keep the CPU performance ball moving forward. FO and FD are integral technologies allowing Intel to overcome challenges with 3D chip stacking and increasing the density of their CPUs. 

FO and FD are new technologies in their second and first generation, respectively.  With every generation of Foverus Omni, Intel has increased the bump density (connection density) by 50%. Whereas, Foverus Direct is a new tech being implemented with Meteor Lake and, has yet to be mass produced.

As mentioned before, these are both new nano technologies developed to address problems with 3D die-to-die stacking, in particular, issues related to power, thermals and interference.  Only the first generation Foverus Omni has been tested by the masses with the release of Intel’s Lakefield processor (2D/3D Hybrid), which was discontinued a year later.  Intel didn’t comment on why Lakefield was canceled, but we do know Lakefield benchmarks were lackluster and 12th Generation Alder Lake was right around the corner. (Source:

Intel museum chip design section

Intel Museum 2019

Credit: David290 via Wikimedia

UCIe Creates New Protocols for Development

3D chip stacking tech is what most major CPU manufacturers are working towards (excluding Nvidia) through the UCIe (Universal Chiplet Interconnect Express) project.  The aim is to design chiplets (or tiles) with universal connectors, allowing manufacturers to mix and match chiplets from different chipmakers. Rather than focus on building all parts of a CPU, chipmakers are collaborating to implement a connection protocol that will make it possible for companies to split up the workloads of building CPUs. As CPUs grow in density, companies like Intel will need to look outward to mitigate the costs associated with building higher density chips. Based on face value alone, the task of building a protocol will be complex, challenging and require a lot of cooperation and innovation among all companies involved.

If Intel is currently trying to implement (in whole or part) UCIe into their 14th generation Meteor Lake line, it is very possible they are running into difficult challenges.  Not only do they have to work on integrating their proprietary chips but, would also need to create the ability to integrate with all other chipmaker’s tiles. This will create more work and require more time for testing, troubleshooting and collaborating.

There are good reasons for the implementation of UCIe which is out-of-scope for this article. The important take-away here is, if Intel is even ‘lightly’ implementing parts of the UCIe protocol, this could undoubtedly create complications to the Meteor Lake production process.

First Generation Disaggregated Chip Design

Disaggregated CPU package design opens the door to allowing multiple companies the ability to manufacture different parts of a CPU. Which differs from the current model, where Intel takes on all the risks and costs associated with creating the entire CPU package.  Disaggregation is important to chipmaking because, one small defect on a chip renders the whole CPU worthless.  As the density of chips increase, the probability of defects rises accordingly.  By breaking the manufacturing process into a chiplet design by disaggregating the CPUs, chipmakers are spreading out the risks of defects and the costs associated with them. Disaggregation is an important technological change that is revamping a decades long process. Another first/second-generation process of development being used in the production of Meteor Lake.


Rumors are swirling about Meteor Lake-S being canceled and desktop Meteor Lake being significantly underpowered when compared to previous statements from Intel.  While we don’t have any solid evidence of a problem or any confirmation that the rumors are true; we just went through some possible reasons why Intel might be struggling with their 14th generation CPU.  We would love to hear from Intel, to say the least.

Nonetheless, Intel has released enough information for us to know they have their work cut out for them.  They are moving from a 10nm process to a 7nm process, disaggregating chips for the second time (after an unimpressive Lakefield Hybrid CPU), stacking chips using 3D stacking technologies for the first & second time, along with adhering to their “Intel 4” process.  These are a lot of fundamental changes converging into one generation of CPUs and, in a very short period of time.

What is unclear, is whether Intel is implementing UCIe or, is even using chips from another manufacturer in this fashion.  If they are, UCIe would undoubtedly add many more complexities to developing and manufacturing the Meteor Lake generation of CPUs.

If the rumors are true, maybe Meteor Lake-S cancellation shouldn’t come to us as a big surprise.  Perhaps it was a mistake to include so many changes into one generation of CPUs.  Maybe this is a necessary learning curve for Intel, to iron out the details for their trillion transistor CPU by 2030.  For now, we will have to wait to see what the future holds.

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